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DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator
October 1988 Revised March 2000
DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator
General Description
The DM96LS02 is a dual retriggerable and resettable monostable multivibrator. The one-shot provides exceptionally wide delay range, pulse width stability, predictable accuracy and immunity to noise. The pulse width is set by an external resistor and capacitor. Resistor values up to 1.0 M reduce required capacitor values. Hysteresis is provided on both trigger inputs of the DM96LS02 for increased noise immunity.
Features
s Required timing capacitance reduced by factors of 10 to 100 over conventional designs s Broad timing resistor range--1.0 k to 2.0 M s Output Pulse Width is variable over a 2000:1 range by resistor control s Propagation delay of 35 ns s 0.3V hysteresis on trigger inputs s Output pulse width independent of duty cycle s 35 ns to output pulse width range
Ordering Code:
Order Number DM96LS02M DM96LS02N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
VCC = Pin 16 GND = Pin 8
Pin Descriptions
Pin Names I0 I0 I1 CD Q Q Description Trigger Input (Active Falling Edge) Schmitt Trigger Input (Active Falling Edge) Schmitt Trigger Input (Active Rising Edge) Direct Clear Input (Active LOW) True Pulse Output Complementary Pulse Output
(c) 2000 Fairchild Semiconductor Corporation
DS009816
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DM96LS02
Functional Description
The DM96LS02 dual retriggerable resettable monostable multivibrator has two DC coupled trigger inputs per function, one active LOW (I0) and one active HIGH (I1). The I1 input and I0 input of the DM96LS02 utilize an internal Schmitt trigger with hysteresis of 0.3V to provide increased noise immunity. The use of active HIGH and LOW inputs allows either rising or falling edge triggering and optional non-retriggerable operation. The inputs are DC coupled making triggering independent of input transition times. When input conditions for triggering are met, the Q output goes HIGH and the external capacitor is rapidly discharged and then allowed to recharge. An input trigger which occurs during the timing cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be terminated (Q to the LOW state) at any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the Q output to I0 or the Q output to I1. Differential sensing techniques are used to obtain excellent stability over temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes pulse width variation from unit to unit. Schottky TTL output stages provide high switching speeds and output compatibility with all TTL logic families.
Logic Diagram
Operation Notes
TIMING 1. An external resistor (RX) and an external capacitor (CX) are required as shown in the Logic Diagram. The value of RX may vary from 1.0 k to 1.0 M. 2. The value of CX may vary from 0 to any necessary value available. If, however, the capacitor has significant leakage relative to VCC/RX the timing equations may not represent the pulse width obtained. 3. The output pulse width tW for RX 10 k and CX 1000 pF is determined as follows: tW = 0.43 RXCX Where RX is in k, CX is in pF, t is in ns or RX is in k, CX is in F, t is in ms. 4. The output pulse width for RX < 10 k or CX < 1000 pF should be determined from pulse width versus CX or RX graphs. 5. To obtain variable pulse width by remote trimming, the following circuit is recommended: TRIGGERING 1. The minimum negative pulse width into I0 is 8.0 ns; the minimum positive pulse width into I1 is 12 ns. 2. Input signals to the DM96LS02 exhibiting slow or noisy transitions can use either trigger as both are Schmitt triggers. 3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable state, input latching is used to inhibit retriggering. 4. An overriding active LOW level direct clear is provided on each multivibrator. By applying a LOW to the clear, any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed. Trigger inputs will not produce spikes in the output when the reset is held LOW. A LOW-to-HIGH transition on CD will not trigger the DM96LS02. If the CD input goes HIGH coincident with a trigger transition, the circuit will respond to the trigger.
6. Under any operating condition, CX and RX (Min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. 7. VCC and ground wiring should conform to good high frequency standards so that switching transients on VCC and ground leads do not cause interaction between one shots. Use of a 0.01 F to 0.1 F bypass capacitor between VCC and ground located near the circuit is recommended.
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DM96LS02
Operation Notes (continued)
Triggering Truth Table
Pin Numbers 5(11) HL H X 4(12) L LH X 3(13) H H L Operation Trigger Trigger Reset
H = HIGH Voltage Level V IH L = LOW Voltage Level VIL X = Immaterial (either H or L) HL = HIGH-to-LOW Voltage Level Transition LH = LOW-to-HIGH Voltage Level Transition
Typical Performance Characteristics
Output tW vs. RX and CX I1 Delay Time vs. TA
I0 Delay Time vs. TA
Output tW vs. TA
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DM96LS02
Typical Performance Characteristics (continued) Normalized tW vs. TA Pulse Width vs. RX CX
Input Pulse f 100 kHz Amp 3.0V Width 100 ns tr = tf 5 ns
FIGURE 1.
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DM96LS02
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 -0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC VT+ VT- Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Positive-Going Threshold Voltage, I0, I1 Negative-Going Threshold Voltage, I0, I1
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VI = 10V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max
Min
Typ (Note 2)
Max -1.5
Units V V
2.7
3.4 0.35 0.25 0.5 0.4 0.1 20 -0.4
V
mA A mA mA mA V V
-20
-100 36 2.0
0.8
5
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DM96LS02
Switching Characteristics
VCC = +5.0V, TA = +25C Symbol tPLH tPHL tPLH tPHL tPHL tPLH Propagation Delay I0 to Q Propagation Delay I0 to Q Propagation Delay I1 to Q Propagation Delay I1 to Q Propagation Delay CD to Q Propagation Delay CD to Q tW(L) tW(H) tW(L) tW(H) tW RX t t I0 Pulse Width LOW I1 Pulse With HIGH CD Pulse Width LOW Minimum Q Pulse Width HIGH Q Pulse Width Timing Resistor Range (Note 4) Change in Q Pulse Width over Temperature Change in Q Pulse Width over VCC Range
Note 4: Applies only over commercial VCC and TA range for 96S02.
Parameter
CL = 15 pF Min Max 55 50 60 55 30 35 15 30 22 25 4.1 1 55 4.5 1000 1.0 0.8 1.5
Units ns ns ns ns ns ns ns ns ns ns s k % %
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DM96LS02
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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